Microvia structure and fabrication

ABSTRACT

A system may include a first microvia pad, a second microvia pad having a projection extending in a direction toward the first microvia pad, and a microvia electrically coupled to the first microvia pad and to the second microvia pad.

BACKGROUND

An integrated circuit (IC) die may include electrical devices that areintegrated within a semiconductor substrate. An IC package is often usedto electrically couple the electrical devices of an IC die to externalcomponents/circuitry. An IC package may also protect an IC die andprovide a suitable operating environment thereto.

An IC package may include layers of conductive paths, or traces, thatcarry signals between an IC die and the external components/circuitry.Microvias within an IC package may electrically couple traces that aredisposed in different layers of the IC package. A microvia may bedrilled into the IC package using a laser and/or may be fabricated usingconventional photolithography. Various factors may cause a microvia todelaminate from surrounding material during operation, therebycompromising the performance and reliability of the IC package.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional side view of an apparatus according to someemmbodiments.

FIG. 2 is a cross-sectional side view of an apparatus according to someembodiments.

FIG. 3 is a diagram of a process to fabricate the FIG. 1 apparatusaccording to some embodiments.

FIG. 4 is a cross-sectional side view of an IC package core illustratinga photolithographic stage according to some embodiments.

FIG. 5 is a cross-sectional side view of an IC package core illustratinga photolithographic stage according to some embodiments.

FIG. 6 is a cross-sectional side view of an IC package core illustratinga photolithographic stage according to some embodiments.

FIG. 7 is a cross-sectional side view of an IC package core illustratinga photolithographic stage according to some embodiments.

FIG. 8 is a cross-sectional side view of an IC package core illustratinga photolithographic stage according to some embodiments.

FIG. 9 is a cross-sectional side view of an IC package core illustratinga photolithographic stage according to some embodiments.

FIG. 10 is a cross-sectional side view of an IC package coreillustrating a photolithographic stage according to some embodiments.

FIG. 11 is a cross-sectional side view of an IC package coreillustrating a photolithographic stage according to some embodiments.

FIG. 12 is a cross-sectional side view of an IC package coreillustrating a photolithographic stage according to some embodiments.

FIG. 13 is a cross-sectional side view of an IC package coreillustrating a photolithographic stage according to some embodiments.

FIG. 14 is a cross-sectional side view of an apparatus according to someembodiments.

FIG. 15 is a cross-sectional side view of an apparatus according to someembodiments.

FIG. 16 is a cross-sectional side view of an apparatus according to someembodiments.

FIG. 17 is a diagram of a process to fabricate the FIG. 15 apparatusaccording to some embodiments.

FIG. 18 is a cross-sectional side view of routing devices attached torespective IC package cores according to some embodiments.

FIG. 19 is a cross-sectional side view of routing devices and an ICpackage core according to some embodiments.

FIG. 20 is a cross-sectional side view of routing devices attached to anIC package core according to some embodiments.

FIG. 21 is a diagram of a system according to some embodiments.

DETAILED DESCRIPTION

FIG. 1 is a cross-sectional side view of a portion of IC package 1. ICpackage 1 may comprise any ceramic, organic, and/or other suitablematerial. IC package 1 may be suitable for receiving an IC die andelectrically coupling the IC die to external components/circuitry.

IC package 1 includes IC package core 10. Core 10 may be composed of anysuitable material, including but not limited to bismalemide triazine(BT) and FR4 in some embodiments. Intermediate layers 30 through 35 maybe composed of dielectric material and/or other material such as BT orFR4. Metallization layers 20 through 27 may include conductive tracesfor routing signals within IC package 1. The conductive traces maycomprise copper or any other suitable conductive material. IC package 10also includes electrical contacts 40 and electrical contacts 50 forelectrically coupling metallization layers 20 through 27 to an IC dieand to a motherboard, respectively. Although electrical contacts 40 andelectrical contacts 50 are illustrated as built-up pads and solderballs, respectively, any suitable electrical contacts may be useddepending upon the system in which IC package 1 is to be used.

A conductive trace within metallization layer 22 may include a microviapad for electrically coupling the trace to a microvia. Such a microviamay exist within intermediate layer 32 between metallization layer 22and metallization layer 23. A conductive trace within metallizationlayer 23 may include a second microvia pad that is also electricallycoupled to the microvia. The microvia may thereby electrically couplethe two conductive traces of the two metallization layers to oneanother.

FIG. 2 is a close-up cross-sectional side view of a portion ofmetallization layer 22, intermediate layer 32, and metallization layer23 according to some embodiments. Metallization layer 22 includesmicrovia pad 60, intermediate layer 32 includes microvia 70, andmetallization layer 23 includes microvia pad 80. Microvia pad 60,microvia 70, and microvia pad 80 are each composed of conductivematerial. Moreover, material 90 disposed between microvia 70 andmicrovia pad 80 also comprises a conductor. Accordingly, microvia 70 iselectrically coupled to microvia pad 60 and microvia pad 80.

Microvia pad 60, microvia 70, and microvia pad 80 may compriseelectrolytic copper. Material 90 may comprise electroless copper toprovide a suitable substrate for the electrolytic copper. Otherconductive materials may be used for microvia pad 60, microvia 70,microvia pad 80, and material 90.

Microvia pad 80 includes base 82 and projection 84 extending therefromtoward microvia pad 60. Projection 84 may be integral to microvia pad80. Projection 84 comprises a plurality of surfaces, including surfaces85 through 87. Microvia 70 includes surfaces 71 through 73 facingrespective ones of surfaces 85 thorough 87. Projection 84 may compriseany three-dimensional shape (e.g. cylinder cube, polyhedra, etc.) havingany number of surfaces. Projection 84 may improve the mechanicalreliability of the interface between microvia 70 and microvia pad 80according to some embodiments.

FIG. 2 shows that metallization layers 22 and 23 might not be ashomogenous as illustrated in FIG. 1. Specifically, metallization layers20 through 27 may include dielectric material, substrate material, othermaterial, as well as metallized conductors.

FIG. 3 is a diagram of process 100 to fabricate microvia 70 according tosome embodiments. Process 100 may be executed by one or more fabricationdevices, and all or a part of process 100 may be executed manually.Process 100 may be executed by an entity different from an entity thatmanufactures an IC die to which IC package 1 is subsequently coupled.

Initially, at 101, a microvia pad is fabricated. The microvia padcomprises a base and a projection extending from the base. FIG. 4 is across-sectional side view of IC package core 10 for illustrating aphotolithographic stage to fabricate a microvia pad according to someembodiments. The microvia pad will be described as fabricated on core10, but may also be fabricated on dielectric material of any ofintermediate layers 30 through 35 of FIG. 1 in some embodiments.

Electroless conductor layer 110 may be deposited on core 10 in order toreceive an electrolytic conductor thereon. Electroless conductor layer110 may comprise copper and may be deposited on core 10 using currently-or hereafter-known techniques for electroless copper deposition. Suchtechniwues include but are not limited to sputtering and chemical vapordeposition. In some embodiments, electroless conductor layer 110 is notused to receive a subsequently-deposited electrolytic conductor.

FIG. 5 illustrates a next photolithographic stage. As shown, photoresist120 is deposited on electroless conductor layer 110, and portionsthereof are selectively removed using any suitable technique such asmasking, UV exposure and stripping. Photoresist 120 may comprise dryfilm, liquid, or other photoresist and may be deposited using anycurrently- or hereafter-known techniques.

Conductive material may then be deposited on the exposed portion oflayer 110 using electroplating techniques. Other deposition techniquesmay also be used in some embodiments. FIG. 6 illustrates conductivematerial 130 deposited on layer 110. Conductive material 130 maycomprise electrolytic copper, and may form a base of a microvia pad.Conductive material 130 may also be deposited elsewhere on layer 110 andwithin metallization layer 23 to form conductive traces in addition tothe base of the microvia pad.

Additional photoresist is then applied as shown in FIG. 7. Photoresist140 may be similar to or different from photoresist 130. As shown,phototresist 140 may be patterned and developed to define opening 150.Conductive material 160 may then be deposited within opening 150 asshown in FIG. 8. Conductive material 160 may comprise electrolyticcopper or another conductive material. Photoresist 130 and 140 may besubsequently removed to result in the structure shown in FIG. 9.Microvia pad 80 includes base 82 and projection 84 extending therefrom.Other methods to fabricate a microvia pad having a base and a projectionextending from the base may be used in some embodiments.

Returning to process 100, a microvia is fabricated at 102. The microviamay have a plurality of surfaces that face a plurality of surfaces ofthe projection fabricated at 101. According to some embodiments of 102,dielectric material 170 is deposited on microvia pad 80 and electrolessconductor layer 110 as shown in FIG. 10. Dielectric material 170 maycomprise any dielectric material suitable for an intermediate layer,including a polymer material. Dielectric material 170 may be laminated,spray coated, or deposited using other techniques.

FIG. 11 shows opening 180 formed in dielectric 170 according to someembodiments. Opening 180 may be formed by laser drilling,photolithography, and/or other techniques. Second electroless conductorlayer 190 may then be deposited in opening 180 and on surroundingstructures as shown in FIG. 12. Second electroless conductor layer 190may be deposited to provide for subsequent deposition of an electrolyticconductor thereon. Accordingly, FIG. 13 illustrates photoresist 200 thathas been deposited, patterned, developed, and removed to create an areaon which to deposit a conductor.

FIG. 14 illustrates 102 after deposition of conductor 210 and removal ofphotoresist 200. Conductor 210 may comprise an electrolytic conductorsuch as electrolytic copper. As described with respect to FIG. 2,conductor 210 comprises microvia pad 60 and microvia 70. Microvia 70includes at least surfaces 71, 72 and 73 which face surfaces 85, 86 and87 of projection 84. After deposition of conductor 210, portions ofsecond conductor layer 190 that are uncovered by conductor 210 may beetched off and replaced by dielectric material as shown in FIG. 2.

FIG. 15 shows microvia pad 220 and microvia 230 according to someembodiments. Both microvia pad 220 and microvia 230 include moreconductive material than pad 60 and microvia 70 of FIG. 2. Currently- orhereafter-known techniques for filling a volume with conductive materialmay be used to create the structure of FIG. 15. The structure of FIG. 15may provide easier planarization than the structure of FIG. 2.

FIG. 16 is a cross-sectional side view of a portion of IC package 300according to some embodiments. IC package 300 includes IC package core305, which may comprise any ceramic, organic, and/or other suitablematerial including bismalemide triazine (BT) and FR4. IC package 300 maybe suitable for receiving an IC die and electrically coupling the IC dieto external components/circuitry.

Metallization layers 310 through 317 may include conductive traces forrouting signals within IC package 300. The conductive traces maycomprise copper or any other suitable conductive material. IC packagecore 305 includes plated through hole 307 to electrically couplemetallization layer 313 to metallization layer 314. Intermediate layers320 through 325 may be composed of dielectric material and/or othermaterial such as BT or FR4.

Intermediate layers 320 through 325 each include at least one ofmicrovias 350 through 358. Microvia 351 includes a first portion and asecond portion, with the first portion having a greater width than thesecond portion. A distance between the first portion and package core305 is less than a distance between the second portion and package core305. In some embodiments, such an arrangement may reduce a possibilitythat microvia 351 may delaminate from a microvia pad located inmetallization layer 311 and/or a microvia pad located in metallizationlayer 312.

Microvia 353 is adjacent to a first side of IC package core 305, andmicrovia 355 is adjacent to a second side of IC package core 305.Microvia 355 includes a third portion and a fourth portion, with thethird portion having a greater width than the fourth portion. A distancebetween the third portion and package core 305 is less than a distancebetween the fourth portion and package core 305. According to someembodiments, one or more intermediate layers might not include amicrovia, and/or a distance between a first portion of one or moremicrovias of IC package 300 and package core 305 may be greater than adistance between a second portion of the one or more microvias andpackage core 305.

IC package 300 includes electrical contacts 330 and electrical contacts340 for electrically coupling metallization layers 310 through 317 to anIC die and to a motherboard, respectively. Although electrical contacts330 and electrical contacts 340 are built-up pads and solder balls,respectively, any suitable electrical contacts may be used dependingupon the system in which IC package 300 is to be used.

FIG. 17 is a diagram of process 400 to fabricate IC package 300according to some embodiments. Process 400 may be executed by one ormore fabrication devices, and all or a part of process 400 may beexecuted manually. Process 400 may be executed by an entity differentfrom an entity that manufactures an IC die to which IC package 300 issubsequently coupled.

A signal routing device is fabricated on a substrate at 401. The signalrouting device includes at least one microvia having a first portion anda second portion. FIG. 18 illustrates signal routing devices 410 and 420as fabricated on respective substrates 411 and 421 according to someembodiments of 401. Routing device 410 includes metallization layers 311through 313 and intermediate layers 320 through 322 as shown in FIG. 16,and routing device 420 includes metallization layers 314 through 316 andintermediate layers 323 through 325. In some embodiments, two signalrouting devices are fabricated on opposite sides of a single substrateat 401. Although two signal routing devices are illustrated in FIG. 8,some embodiments of process 400 are executed in conjunction with asingle signal routing device.

Substrates 411 and 421 may comprise any suitable base on whichelectrical elements may be fabricated. Examples include a work surfacesuch as a glass or metal wafer chuck, BT or FR4 substrate material, orother substrate materials. Substrates 411 and 421 may be coated withrespective release layers 412 and 422 prior to fabricating signalrouting devices 410 and 420 thereon. Release layers 412 and 422 maycomprise a release film or any other currently- or hereafter-knownrelease layer composition.

Signal routing devices 410 and 420 are then fabricated on release layers412 and 422 according to currently- or hereafter-known systems forfabricating routing devices that include layers of traces, interlayerdielectric material, and vias between the layers of conductive traces.According to some embodiments, process 100 is used to fabricate routingdevices 410 and 420.

Signal routing devices 410 and 420 are then removed from substrates 411and 421 at 402. Removal may include peeling signal routing devices 410and 420 and respective release layers 412 and 422 from substrates 411and 421. In some embodiments, release layers 412 and 422 are dissolvedat 402, thereby removing signal routing devices 410 and 420 fromsubstrates 411 and 421. FIG. 19 shows signal routing devices 410 and 420after being removed from substrates 411 and 421 according to someembodiments.

Next, at 403, signal routing devices 410 and 420 are attached to an ICpackage core. FIG. 20 illustrates signal routing devices 410 and 420 asattached to IC package core 305 according to some embodiments. Signalrouting devices 410 and 420 may be laminated to IC package core 305 at403. Signal routing device 410 is attached to IC package core 305 suchthat a distance between a first portion of at least one microvia ofdevice 410 and package core 305 is less than a distance between a secondportion of the at least one microvia and package core 305, the firstportion being wider than the second portion. Similarly, signal routingdevice 420 is attached to IC package core 305 such that a distancebetween a first portion of at least one microvia of device 420 andpackage core 305 is less than a distance between a second portion of theat least one microvia and package core 305, with the first portion againbeing wider than the second portion.

According to some embodiments, release layers 412 and 422 are strippedfrom routing devices 410 and 420 after 403. Then, metallization layers310 and 317 are added to package 300 along with electrical contacts 330and 340 as illustrated in FIG. 16.

FIG. 21 is a side elevation of system 500 according to some embodiments.System 500 may comprise components of a server platform. System 500includes IC package 300 as described above, IC die 510, memory 520 andmotherboard 530. IC die 510 may comprise a microprocessor.

Motherboard 530 may electrically couple memory 520 to IC package 300.More particularly, motherboard 530 may comprise a memory bus (not shown)that is electrically coupled to electrical contacts 340 and to memory520. Memory 520 may comprise any type of memory for storing data, suchas a Single Data Rate Random Access Memory, a Double Data Rate RandomAccess Memory, or a Programmable Read Only Memory.

The several embodiments described herein are solely for the purpose ofillustration. The various features described herein need not all be usedtogether, and any one or more of those features may be incorporated in asingle embodiment. Some embodiments may include any currently orhereafter-known versions of the elements described herein. Therefore,persons skilled in the art will recognize from this description thatother embodiments may be practiced with various modifications andalterations.

1. An apparatus comprising: a first microvia pad; a second microvia padhaving a projection extending in a direction toward the first microviapad; and a microvia electrically coupled to the first microvia pad andto the second microvia pad.
 2. An apparatus according to claim 1,wherein the microvia includes a plurality of surfaces facing a pluralityof surfaces of the projection.
 3. An apparatus according to claim 1,wherein the projection is an integral portion of the second microviapad.
 4. An apparatus according to claim 1, further comprising: anelectroless conductor disposed between the microvia and the secondmicrovia pad, wherein the second microvia pad and the microvia arecomposed of an electrolytic conductor.
 5. An apparatus according toclaim 1, further comprising: an integrated circuit package including aplurality of metallization layers, wherein a first one of themetallization layers includes the first microvia pad, and a second oneof the metallization layers includes the second microvia pad.
 6. Anapparatus comprising: a first microvia pad; a second microvia pad; and amicrovia electrically coupled to the first microvia pad and to thesecond microvia pad, the microvia including a plurality of surfacesfacing respective ones of a plurality of surfaces of the second microviapad.
 7. An apparatus according to claim 6, further comprising: anelectroless conductor disposed between the microvia and the secondmicrovia pad, wherein the second microvia pad and the microvia arecomposed of an electrolytic conductor.
 8. An apparatus according toclaim 6, further comprising: an integrated circuit package including aplurality of metallization layers, wherein a first one of themetallization layers includes the first microvia pad, and a second oneof the metallization layers includes the second microvia pad.
 9. Amethod comprising: fabricating a microvia pad having a base and aprojection extending from the base; and fabricating a microvia having aplurality of surfaces facing a plurality of surfaces of the projection.10. A method according to claim 9, further comprising: fabricating anelectroless conductor disposed between the microvia and the microviapad, wherein the microvia pad and the microvia are composed of anelectrolytic conductor.
 11. A method according to claim 10, whereinfabricating the microvia pad comprises: fabricating the base; andfabricating the projection extending from the base after fabricating thebase.
 12. A system comprising: an integrated circuit package comprising:a first microvia pad; a second microvia pad having a projectionextending in a direction toward the first microvia pad; and a microviaelectrically coupled to the first microvia pad and to the secondmicrovia pad; and a double data rate memory electrically coupled to theintegrated circuit package.
 13. A system according to claim 12, whereinthe microvia includes a plurality of surfaces facing a plurality ofsurfaces of the projection.
 14. A system according to claim 12, whereinthe projection is an integral portion of the second microvia pad.
 15. Asystem according to claim 12, further comprising: a motherboardelectrically coupled to the integrated circuit package and to thememory.
 16. An apparatus comprising: an integrated circuit package core;and a microvia having a first portion adjacent to a first microvia padand a second portion adjacent to a second microvia pad, a width of thefirst portion being greater than a width of the second portion, whereina distance between the first portion and the integrated circuit packagecore is less than a distance between the second portion and theintegrated circuit package core.
 17. An apparatus according to claim 16,further comprising: a second microvia having a third portion adjacent toa third microvia pad and a fourth portion adjacent to a fourth microviapad, a width of the third portion being greater than a width of thefourth portion, wherein a distance between the third portion and theintegrated circuit package core is less than a distance between thefourth portion and the integrated circuit package core.
 18. An apparatusaccording to claim 17, wherein the first microvia is adjacent to a firstside of the integrated circuit package core, and the second microvia isadjacent to a second side of the integrated circuit package core.
 19. Anapparatus according to claim 16, further comprising: a plurality ofmetallization layers, wherein a first one of the metallization layersincludes the first microvia pad, and a second one of the metallizationlayers includes the second microvia pad.
 20. A method comprising:fabricating a signal routing device on a substrate, the signal routingdevice comprising a microvia having a first portion and a secondportion, a width of the first portion being greater than a width of thesecond portion; removing the signal routing device from the substrate;and attaching the signal routing device to an integrated circuit packagecore, wherein a distance between the first portion of the microvia andthe integrated circuit package core is less than a distance between thesecond portion of the microvia and the integrated circuit package core.21. A method according to claim 20, wherein the signal routing device isattached to a first side of the integrated circuit package core, themethod further comprising: fabricating a second signal routing device ona second substrate, the second signal routing device comprising a secondmicrovia having a third portion and a fourth portion, a width of thethird portion being greater than a width of the fourth portion; removingthe second signal routing device from the second substrate; andattaching the second signal routing device to a second side of theintegrated circuit package core, wherein a distance between the thirdportion of the microvia and the integrated circuit package core is lessthan a distance between the fourth portion of the microvia and theintegrated circuit package core.
 22. A method according to claim 20,wherein the signal routing device is attached to a first side of theintegrated circuit package core, the method further comprising:fabricating a second signal routing device on the substrate, the secondsignal routing device comprising a second microvia having a thirdportion and a fourth portion, a width of the third portion being greaterthan a width of the fourth portion; removing the second signal routingdevice from the substrate; and attaching the second signal routingdevice to a second side of the integrated circuit package core, whereina distance between the third portion of the microvia and the integratedcircuit package core is less than a distance between the fourth portionof the microvia and the integrated circuit package core.
 23. A methodaccording to claim 20, wherein fabricating the signal routing device onthe substrate comprises fabricating the signal routing device on arelease layer attached to the substrate.
 24. A system comprising: anintegrated circuit package comprising: an integrated circuit packagecore; and a microvia having a first portion adjacent to a first microviapad and a second portion adjacent to a second microvia pad, a width ofthe first portion being greater than a width of the second portion,wherein a distance between the first portion and the integrated circuitpackage core is less than a distance between the second portion and theintegrated circuit package core; and a double data rate memoryelectrically coupled to the integrated circuit package.
 25. A systemaccording to claim 24, the integrated circuit package furthercomprising: a second microvia having a third portion adjacent to a thirdmicrovia pad and a fourth portion adjacent to a fourth microvia pad, awidth of the third portion being greater than a width of the fourthportion, wherein a distance between the third portion and the integratedcircuit package core is less than a distance between the fourth portionand the integrated circuit package core.
 26. A system according to claim25, wherein the first microvia is adjacent to a first side of theintegrated circuit package core, and the second microvia is adjacent toa second side of the integrated circuit package core.
 27. A systemaccording to claim 24, further comprising: a motherboard electricallycoupled to the integrated circuit package and to the memory.